A Novel High Speed Simulated Annealing Algorithm for Non-Slicing VLSI Floorplanning using B*-Tree Representation
نویسندگان
چکیده
منابع مشابه
Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary
Floorplan representation is a fundamental issue in designing a VLSI floorplanning algorithm as the representation has a great impact on the feasibility and complexity of floorplan designs. This survey paper gives an up-to-date account on various nonslicing floorplan representations in VLSI floorplanning.
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ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2016
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2016/v9i48/94334